The present invention relates to semiconductor memories and, more particularly, to electronically nonvolatle stored charge semiconductor memories adapted for use in an extremely high density integrated circuit memory array structure.
Field effect transistors utilizing charges stored in dual insulators overlying the channel of the FET are known to the art. In these field effect transistors the basic gate dielectric structure of the FET is provided with a carrier trapping interface between a first insulator, usually an oxide, and a second insulator, usually a trapping material having different dielectric properties. Silicon nitride and silicon dioxide dielectric materials are commonly employed in combination as the two insulators.
Such charge accumulation is due to the different conductivities of the layers and is retained in the insulating layers when the applied voltage is removed because the current densities in the layers are nonlinear functions of the electric field intensity.
Since the present invention relates particularly to diffused semiconductor structures utilizing metallic lines overlying the diffusion and insulated therefrom by a dual insulator structure, it should be mentioned that there are still other structures which are not field effect transitors that utilize dual insulators and diffusions in semiconductor bodies. For example, IBM Technical Disclosure Bulletin, Volume 12, No. 1, June, 1969, on Page 202, described a capcative storage cell utilizing diffusions in a semiconductor body which diffusions are covered by metallic lines insulated from the diffusions by layers of silicon dioxide and silicon nitride. IBM Technial Diclosure Bulletin, Volume 14, No. 12, May, 1973, discloses a single diffusion metal-nitride-oxide semiconductor device which utilizes trapping in the oxide layer by causing the surface adjacent to the diffusion to be either inverted or noninverted thus varying the capacitance of the diffusion. U.S. Pat. No. 3,446,955 teaches that the breakdown voltage of a junction diode can be varied by applying a suitable bias to an electrode overlying, but insulated from the junction. U.S. Pat. No. 3,428,875 teaches that the flatband voltage of an MOS capacitor can be precisely varied by placing two layers of different dielectric material between the body of the semiconductor material and the overlying gate electrode.
U.S. Pat. No. 3,838,405, filed by the inventors of the present application and entitled "Nonvolatile Diode Cross Point Memory Array," discloses a semiconductor integrated circuit memory structure utilizing word and bit lines orthogonally disposed with respect to each other and wherein stored carriers injected into the region adjacent to the crossover area by biasing the junctions formed to avalanche breakdown conditions wherein the read-out operation occurs as a result of opposite biasing to break down in the opposite direction to provide read-out. The structure disclosed in this patent is similar to that of the instant invention but differs in the doping levels within the bit lines and in the surface of the semiconductor body adjacent to the oxide layer. The result is that in the patented device the carrier storage occurs in a region adjacent to but essentially outside of the word and bit line intersection areas. Thus the ultimate density of such an array is limited by this fringing effect. Further, in certain circumstances, the read-out operation can in turn cause considerable degradation of the carriers stored in the device limiting the non-volatile life of the cell.